Coherent Accelerator Processor Interface (CAPI) for POWER8

The majority of computational accelerator systems use PCI Express to connect to the main processor units via the IO subsystem. IBM has devised CAPI as an alternative that removes the complexity and overhead of the IO subsystem to enable higher system performance.

The reconfigurability of Xilinx FPGAs allows CAPI to be implemented on existing PCI Express based accelerators using the Power Service Layer (PSL).

Alpha Data and CAPI

“Coherent Accelerator Processor Interface (CAPI) removes the software overhead for processor communication with the I/O subsystem, allowing an accelerator to operate as part of an application. CAPI on POWER8 systems provides a high-performance solution for the implementation of client-specific, computation-heavy algorithms on an FPGA. IBM’s solution enables higher system performance with a much smaller programming investment, allowing hybrid computing to be successful across a much broader range of applications.”

Brad McCredie – OpenPOWER Foundation President and IBM Fellow

“Alpha Data is working closely with Xilinx to accelerate innovation. Xilinx recently demonstrated a 36X performance/watt improvement on a Big Data application with an IBM POWER8 system and Alpha Data’s CAPI development kit. The collaboration between Alpha Data, Xilinx, IBM, and the OpenPOWER Foundation is producing breakthrough performance using Xilinx All Programmable FPGAs.”

Hemant Dhulla, vice president of wired communications and data center at Xilinx.

OpenPOWER Organisation LOGO

Alpha Data is a member of the OpenPOWER™ Foundation and has worked with fellow members Xilinx and IBM to provide CAPI reference designs for the ADM-PCIE-7V3, ADM-PCIE-KU3 and ADM-PCIE-8K5 accelerator boards.

CAPI - Variants Overview

CAPI 1.0/2.0

The original CAPI architecture which uses PCI Express as its transport layer. CAPI provided both a hardware and software wrapper around the PCI Express interface which simplified the users access to the adaptor cards memory/accelerator functionality.

CAPI 1.0 operated on PCI Express Gen3 x8 providing up to 4GB/s data throughput.

CAPI 2.0 operated on PCI Express Gen3 x16 providing up to 15.75GB/s data throughput.





ADM-PCIE-9H7 - CAPI 2.0 (In development)

OpenCAPI 3.0

In order to minimise latency and reduce protocol overheads OpenCAPI was developed. Instead of, as in CAPI 1.0/2.0, of using PCI Express as the transport layer OpenCAPI has a separate interface based on 8x25.78Gbps interface.

ADM-PCIE-9V3 - 1 OpenCAPI interface

ADM-PCIE-9H3 - 1 OpenCAPI interface (In development)

ADM-PCIE-9H7 - 2 OpenCAPI Interfaces (In development)

For further details on OpenPOWER :

Visit the OpenPOWER Foundation Website

Read Coherent Accelerator Processor Interface (CAPI) for POWER8 Systems - White Paper (PDF)

Read Data Engine for NoSQL IBM Power Systems™ Edition - White Paper (PDF)

Read Coherent Accelerator Processor Interface (CAPI) for POWER8 Systems Decision Guide and Development Process (PDF)

Read Coherent Accelerator Processor Interface Reference Design User Guide (PDF)

CAPI Based Block Diagram
Flow Diagram for CAPI System

COMING SOON : OpenCAPI Connectivity

ADM-pCIE-9V3 ina Barreleye Server connected by OpenCAPI

An ADM-PCIE-9V3 connected via OpenCAPI in a Barreleye Server.

Further Information

Contact Alpha Data for further details on our CAPI reference designs: Email

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