Partial Reconfiguration Based Design Flow Overview

The following diagram outlines the design flow to utilise partial reconfiguration on Alpha Data FPGA boards.

This flow allows multiple user designs to be configured in an FPGA without the need to reboot the host system between configurations. It is essential that all user designs use the same PCI Express configuration (number and size of BARs and number of interrupts as well as the same user design interface).

Partial Reconfiguration Flow Diagram

As all designs created in this flow use the same PCI Express configuration only the "User Design" BIT file needs to be loaded into the FPGA and this can be performed at runtime, via PCI Express, with no need to reboot the system.

Partial Reconfiguration FPGA Block Diagram

Further Information

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