Specification
Board Format
3U VPX (SOSA Aligned - VITA 46 and 65)
Width: 100 mm
Height: 19.55 mm
Depth: 160 mm
Weight: TBD g
Environmental Specifications
Temperature Limits | Operating Temperature Range | Storage Temperature Range |
---|
Min | Max | Min | Max |
---|
AC1 | Air Cooled Industrial | -40°C | +70°C | -55°C | +100°C |
CC1 | Conduction Cooled Industrial | -40°C | +85°C | -55°C | +100°C |
Operating Humidity Range:
Up to 95% (non-condensing)
Host I/F
Default: Ethernet (40G)
Alternate: PCI Express Gen3 x8
Target Device
AMD Zynq® Ultrascale+
XCZU11EG-2 (FFVF1517)
FPGA Resources
Chosen Device | DSPs | BRAM | URAM |
---|
XCZU11EG-2 | 2928 | 21.1Mb | 22.5Mb |
FPGA Hard IP Cores
4x ARM® Cortex™-A53 MPCore™ - 1.5GHz
2x ARM® Cortex™-R5 MPCore™ - 600MHz
1x PCIe Gen3x8 in PL
1x PCIe Gen2x4 to ARM PS
On Board Memory
Memory Type | No. Banks | Memory Size (per bank) |
---|
SDRAM | 1 | 32Gb DDR4 - 8GB @ 72-bit wide (Connected to PS) |
SDRAM | 2 | 8Gb DDR4 - 4GB @ 32-bit wide (Connected to PL) |
microSD | 1 | SD Card specific SDC - (Connected to Ps) |
EMMC | 1 | 32GB EMMC - (Connected to Ps) |
Target FPGA Configuration
PS - Configured via QSPI, uSD or EMMC
FPGA Configuration Flash
Flash Type | Flash Size |
---|
QSPI | 2048Mb |
On-board Clock Specifications
250MHz Reference Clock- HSSIO MGTs100MHz - PCI Express Reference CLockProgrammable Clock (150MHz default)300MHz Reference Clock (DDR4)300MHz Fabric Clock25MHz Reference Clock (Ethernet)50MHz Reference Clock (PS Core)
I/O Interfaces
Interface Type | Qty | Description |
---|
DISCRETE I/O (XRM I/O) |
XRM IO | 8 | HSSIO Links |
XRM IO | 146 | LVCMOS/LVDS IO |
P1 COMMUNICATIONS I/O (P1) |
Expansion Plane (PCI Express) | 1 | Gen2 x4 or Gen3 x8 (G2x4 from PS or G3x4/x8 from PL) |
Ethernet | 1 | 40G Fat Pipe Ethernet |
Ethernet | 2 | 1G/10G Ultra Thin Pipe Ethernet |
Serial Low-Speed Comms | 2 | RS232 or UART from PS |
P0 COMMUNICATIONS I/O (P0) |
Serial Low-Speed Comms | 2 | IPMC compliant redundant I2C |
Serial Low-Speed Comms | 1 | JTAG programming interface |