Specification
Board Format
PCIe 3/4 Length, full height, Dual Slot, includes front panel
Width: 267.2 mm
Height: 126.3 mm
Depth: 39.9 mm
Environmental Specifications
Temperature Limits | Operating Temperature Range | Storage Temperature Range |
|---|
| Min | Max | Min | Max |
|---|
| Active | FAN Fitted | 0°C | +55°C | -40°C | +85°C |
| Passive | FAN not Fitted | 0°C | +55°C | -40°C | +85°C |
Operating Humidity Range:
Up to 95% (non-condensing)
EMC:
See the ADM-PA120 Declaration of Conformity document
Host I/F
Dual PCI Express Gen5 x8
Target Device
AMD Versal™ Premium Adaptive SoC
VP1202, VP1502 (A2785)
FPGA Resources
| Chosen Device | LUTs | DSPs | BRAM | URAM |
|---|
| VP1202 | 900.2k | 3984 | 47Mb | 190Mb |
| VP1502 | 1720k | 7440 | 89Mb | 366Mb |
FPGA Hard IP Cores
2x ARM Cortex-A72 MPCore™
2x ARM Cortex-R5F MPCore™
1x 256kB On-Chip Memory with ECC
On Board Memory
| Memory Type | No. Banks | Memory Size (per bank) |
|---|
| LPDDR4-SDRAM | 4 | 512M x 64bit (4GiB) LPDDR4-3733 |
System Monitor
The ADM-PA120 provides a system monitoring chip which can provide real-time temperature, voltage and current readings of the system, as well as reconfigure programmable clocks and much more. The system monitor can be accessed directly through the USB interface via the front panel (or rear of the board). It also connects to the target FPGA via the USB to UART interface (see block diagram).
Target FPGA Configuration
The FPGA is configurable using a front panel USB interface and the Vivado tool suite (through the onboard digilent module).The configuration flash for the FPGA is writeable via the USB interface and the Vivado tool suite, or the provided Alpha Data Firmware.
FPGA Configuration Flash
| Flash Type | Flash Size |
|---|
| x8 QSPI | 4Gb (2x 2Gb devices) |
I/O Interfaces
| Interface Type | Qty | Description |
|---|
| FRONT I/O (Front Panel) |
| QSFP-DD | 1 | 3x QSFP-DD Cages for copper or fibre interconnectivity. Capable of up to 28Gbps NRZ (all QSFP-DD cages) or 56Gbps PAM4 (2 of the QSFP-DD cages). |
| TIMING I/O I/O (Front Panel) |
| 10MHz external input clock | 1 | 10MHz input (ITU-T G.703 section 20 compliant) |
| 1PPS Input | 1 | 1PPS timing input (ITU-T G.703 section 19.2 compliant) |
| 1PPS Output/Trigger Output | 1 | 1PPS timing output (ITU-T G.703 section 19.2 compliant) |
| Time Of Day (ToD) | 1 | RJ45 Connector for ToD and 1PPS input/Output (ITU-T G.703 section 19. compliant) |
