Summary

The ADM-XRC-7V1 is a high performance reconfigurable XMC (compliant to VITA Standard 42.0 and 42.3) based on the AMD Virtex-7 range of Platform FPGAs.

Features include PCI Express Gen2 interface, external memory, high density I/O, system monitoring and flash boot facilities.
A comprehensive cross platform API with support for Microsoft Windows, Linux and VxWorks provides access to the full functionality of these hardware features.
Placing the PCI Express bridge in bypass allows the creation of a Gen 2 x8 PCI Express endpoint design directly into the target FPGA. Target FPGAs VX330T and VX690T can also support Gen3 x8 PCI Express designs.
The optional fitting of the Pn4 connector provides an additional 64 General Purpose IO (GPIO) links to the carrier card.
The ADM-XRC-7V1 is available in a cost reduced form for high-volume production orders (the build option removes the Virtex-6 Bridge device).

Applications

Digital Signal Processing
Radar/Sonar Beamforming
ELINT
Image/Video Processing
Data Encryption

Board Features

Air-Cooled/Conduction-Cooled Options
Separate PCI Express Bridge
XRM2 I/O Interface

FPGA Features (Hard IP)

2x PCI Express cores (Gen2 or Gen3 - FPGA dependent)

Specification

Board Format

XMC (Switched Mezzanine Card, VITA 42)

Environmental Specifications

Temperature Limits
Operating Temperature RangeStorage Temperature Range
MinMaxMinMax
AC0Air Cooled Commercial0°C+55°C-40°C+85°C
ACEAir Cooled Extended0°C+70°C-55°C+100°C
AC1Air Cooled Industrial-40°C+70°C-55°C+100°C
CC0Conduction Cooled Commercial0°C+55°C-40°C+85°C
CCEConduction Cooled Extended0°C+70°C-55°C+100°C
CC1Conduction Cooled Industrial-40°C+70°C-55°C+100°C

Operating Humidity Range:
Up to 95% (non-condensing)


Host I/F

PCI Express Gen2 x1, x2 or x4 link to separate bridge device with 2GB/s local link to user FPGA
4 DMA Controllers
Interrupt Controller


Target Device

AMD Virtex® -7
XC7V585T, XC7VX485T, XC7VX690T (FF(G)1761, FH(G)1761 or FLG(G)1761)

FPGA Resources

Chosen DeviceFFsLUTsDSPsBRAM
XC7V585T728k582k126028Mb
XC7VX485T607k485k280037Mb
XC7VX690T866k693k360052Mb

FPGA Hard IP Cores

2x PCI Express cores (Gen2 or Gen3 - FPGA dependent)

On Board Memory options

Memory TypeNo. BanksMemory Size (per bank)
SDRAM4512MB DDR3-1600
1GB DDR3-1600

Target FPGA Configuration

PCI Express direct to SelectMAP port
From Flash direct on power up
External JTAG connector


FPGA Configuration Flash

Flash TypeFlash Size
BPI512MBit

On-board Clock Specifications

Low-jitter 250MHz reference clock, suitable for SerDes applications
Low-jitter 200MHz reference clock for IOB delay circuits
Custom clock inputs available through the XRM2 interface
Two Software-Programmable Clocks


I/O Interfaces

Interface TypeQtyDescription
FRONT I/O (XRM2)
Discrete Digital146LVCMOS/LVDS I/O (programmable to 1.2, 1.5 or 1.8V)
High-Speed
Serial Links
8High-Speed Serial Links to XRM2
REAR I/O (Pn6)
High-Speed
Serial Links
10High-Speed Serial Links via Pn6 connector
Discrete Digital38LVCMOS 3.3V GPIO connections via Pn6 connector (VITA 46.9 X8d+X12d+X38s compatible pinout)
REAR I/O (Pn4)
Discrete Digital64Multiple LVCMOS/LVDS GPIO connections via optional PMC Pn4 connector (1.8V levels with 2.5V compatible inputs)
only available with Pn4 Build Option selected

Ordering Information

Ordering Code
ADM-XRC-7V1/z-y(m)(c)(a)(p)(t)
ParameterCodeParameter Description
Virtex-7 devicezV585T=XC7V585T,
VX485T=XC7VX485T,
VX690T=XC7VX690T
Virtex-7 speedy1, 2, 3
Memorymblank = 2GBytes on board SDRAM (Four banks of 512MBytes),
/4 = 4GByte on board SDRAM (Four banks of 1GByte)
Coolingcblank = air cooled commercial,
/ACE = air cooled Extended,
/AC1 = air cooled industrial,
/CC0 = conduction cooled Commercial,
/CCE = conduction cooled Extended,
/CC1 = conduction cooled industrial
Conformal Coatingablank = no conformal coating,
A = Acrylic,
P = Polyurethane
Pn4 Fittedpblank = not fitted,
/Pn4 = Pn4 Connector fitted
XMC Connector Typetblank = XMC (VITA 42) Connectors ,
/X2 = XMC2 (VITA 61) Connectors
Notenot all FPGA speed grades available in all configurations.
Contact Alpha Data for full details.

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