White Papers and Application Notes
Supporting Analog Devices AD9361 on the ADM-XRC-9Z1 (ad-an-0152,ad-an-0153)
The ADM-XRC-9Z1 is a versatile system-on-module XMC which can provide comprehensive processing solution featuring a CPU Processing System and FPGA Programmable Logic in the ZU11EG MPSoC device. This product can be enhanced with the addition of an XRM2-RF-ATD IO module featuring the AD9361 agile transceiver. This application note documents how to use this board combination and deploy the Analog Devices reference firmware and software examples and libraries for the AD9361 on the ARM CPU and PL of the Zynq Ultrascale+ MPSoC device. A second application note demonstrating how to deploy these designs on the ADM-XRC-7Z1 is also available.
Download ADM-XRC-7Z1 AppNote here
Download ADM-XRC-9Z1 AppNote here
Vibration Testing of the ADM-VPX3-9Z5 (ad-an-0134)
This white paper provides an overview of the vibration testing of the Alpha Data ADM-VPX3-9Z5 board. It documents the test standards used and the relevant report confirming that the board withstood the testing levels stipulated by the adopted standard.
The purpose of this vibration test was to subject the board to conditions typical of a low Earth Orbit Space launch as well as in excess of other in-atmosphere rugged deployment environments, and verify that it can operate after exposure to such conditions.
Exercising Vitis AI Applications on Alpha Data Boards (ad-an-0131)
The Xilinx Deep Learning Processor Unit (DPU) is a configurable computation engine intended for convolutional neural networks. It includes a set of highly optimised instructions and supports most convolutional neural networks. The Xilinx Vitis AI is a development stack for AI inference on Xilinx hardware platforms and Vitis AI applications are built on top of extensible Vitis platforms by integrating one or more DPUs as kernel.
This paper provides an overview of the requirements for exercising Vitis-AI applications on Alpha Data boards. It documents the Vitis base platform build process and the flow for a typical Vitis-AI application build and execution, using the Resnet50 as an example.
Space Tolerant CNN FPGA Deployment (ad-an-0116, ad-an-0117, ad-an-0118, ad-an-0119)
This is a 4 part paper series providing an educational overview of the issues surrounding the deployment of Convolutional Neural Network solutions on FPGAs in radiation susceptible environments. The first part documents a small but practical CNN processing core suitable as a sub-system in a large FPGA design. The second part discusses the space hardening of this core adding in triple mode redundancy, for radiation effect tolerance, to control path circuitry. The third part documents higher level control structures needed to move data to and from the core and dynamically reconfigure its operation. The fourth part documents the deployment of this design on the Alpha Data ADA-SDEV-KIT3 Space Development Kit for the Xilinx XQRKU060 FPGA device.
Download the code here (github)
Modified-COTS (MCOTS) : Modified Commercial Off The Shelf (mcots_overview)
Alpha Data offers an extensive catalog of commercial-of-the-shelf products suitable for both prototyping and deployment. However, many customers require changes to the form or function in order to meet their specific requirements.
Modified-COTS (MCOTS) is a service provided by Alpha Data that reuses existing designs, enabling customers to receive a product that fully meets their needs with minimum NRE cost and risk. Furthermore, existing COTS products can be used to develop much of the final functionality while the MCOTS product is designed and manufactured.
Hyperspectral Imaging and Compression Solutions (ad-an-0075)
JPL, in collaboration with Alpha Data Parallel Systems (Alpha Data), has developed a real-time capable FLEX compression core for Hyperspectral data – targeting various Alpha Data COTS and MCOTS products. Alpha Data now offer COTS and MCOTS FPGA based Hyperspectral acquisition and compression solutions licenced with the JPL FLEX compression core(s).
Breaking Memory Bandwidth Barriers using High Bandwidth Memory FPGA (ad-an-0066)
The release of Virtex Ultrascale+ High Bandwidth Memory(HBM) FPGA devices, opens up whole new areas of memory bound applications to the benefit of power efficient FPGA acceleration. A recent increasing trend has been to target a variety of memory bound applications to GPU systems, simply because of their significant memory bandwidth advantage over the CPU, and this is despite the application not having any need for the GPUs primary functionality: the very high performance parallel floating point arithmetic. With the advent of FPGAs with similar external memory bandwidth, but much more flexible and higher internal memory bandwidth configurability, more customized and energy efficient accelerated solutions for these problems are now possible.
An Open Source FPGA CNN Library (ad-an-0055)
Convolutional neural networks have become the core component of a large number of hyperscale deployed machine learning algorithms used in image and vision recognition tasks. Low-bitwidth FPGA implementations of these networks provide a potential path to higher throughput and lower power machine learning inference solutions.
One purpose of this toolbox is to provide an easy path for developers to investigate the accuracy implications of switching from floating point defined network weights to low bitwidth fixed point weights on each of the layers making up the network
Another purpose of this toolbox is to provide tools and knowledge for comparing network structure and size with on-chip memory and processing capabilities of FPGAs to aid in optimal device selection.
See full paper here (ad-an-0055)
Download the code here (github)
FPGA based Volume Ray-Casting (vrc_2017_final_2)
This paper outlines how a compute-intensive algorithm can be implemented on a FPGA card with a PCI Express interface, utilising Vivado HLS and Alpha Data’s ADB3 PCIe Bridge. The presented system is shown to be scalable and power efficient.
The FPGA platform is built from a combination of a top-level IP Integrator (IPI) system, IP cores for on/off-chip data flow and board-specific host communications. These are combined with the ray-casting IP cores written in C++ and synthesised with Xilinx’s Vivado HLS tool. Some important aspects of these IP are discussed.
