- High Performance Reconfigurable Computing
- High Performance Reconfigurable Computing
AD01385
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ADM-PCIE-9V5 Documents
Please contact Alpha Data for details on the purchase of the ADM-PCIE-9V5 SDK.
Applications
Board Features
FPGA Features (Hard IP)
Summary
The ADM-PCIE-9V5 is a Single-slot half-length, full height, PCI Express Add-In Card featuring the powerful and efficient Xilinx Virtex UltraScale Plus VU9P-3 FPGA.
8 lane PCIe Gen3 capable Interface.
Front IO with 4x QSFP-DD sockets, each supporting two 100GbE or eight 10/25GbE interfaces. Onboard Ultraport SlimSAS Connector for OpenCAPI Connectivity.
System monitoring of temperature, voltage, and current gives developers accurate feedback of power utilization for their designs.
Board Format
Single Slot 1/2 Length, Full Height, x8 PCIe form Factor
Width: TBCmm Height: TBCmm Depth: TBCmm Weight: TBCg
Environmental Specifications
Temperature Limits:
Operating Temperature range: 0°C to +55°C
Storage Temperature range: -40°C to +85°C
Operating Humidity range: Up to 95% (non-condensing)
Host I/F
PCI Express® Gen3 x8 or OpenCAPI
Target Device
Xilinx Virtex® UltraScale Plus™
XCVU9P-3 or XCVU5P-3 - FLGA2104/FLVA2104
FPGA Resources
| Chosen Device | FFs | LUTs | DSPs | BRAM | URAM |
|---|---|---|---|---|---|
| XCVU9P-3 | 2364k | 1182k | 6840 | 75.9Mb | 270.0Mb |
| XCVU5P-3 | 1201k | 601k | 3474 | 36Mb | 132.2Mb |
FPGA Hard IP Cores
Note: for the FPGA packages used for this product, certain GTY tiles are unavailable because they are not bonded to physical pins. This means that, in order to make use of certain hard CMAC, PCIe and Interlaken cores, the 'Pipe' scheme must be used, in which the core in question is routed to bonded GTY tile(s) using pipelining registers.
For diagrams showing bonded and unbonded GTY tiles, please refer to Figures 1-90 (VU5P in FLV2104 package) and 1-99 (VU9P in FLGA2104 package) in UG575-ultrascale-pkg-pinout.pdf (v1.13)
Board Management
The ADM-PCIE-9V5 houses a system monitoring chip which is able to provide real-time temperature, voltage and current readings of the system, as well as reconfigure programmable clocks and much more. The system monitor can be accessed directly through the USB interface via the front panel (or rear of board), the UART connection to the target FPGA or through the SMBus interface on the card's PCI Express edge connector. When enabled**, IPMI can also be used to communicate with the system monitor, allowing for remote communication and management with the ADM-PCIE-9V5.
** IPMI is disabled by default and should only be enabled when the board is installed in an IPMI compliant system. Please contact the factory for details on enabling IPMI on the ADM-PCIE-9V5.
FPGA Configuration
The USB/JTAG Interface is compatible with all of the Xilinx Vivado® Tools.
FPGA Configuration Flash
| Flash Type | Flash Size | No. config regions |
|---|---|---|
| QSPI | 2GBit | each of |
High-Speed Network Interfaces
| Interface Type | Qty | Lanes per Interface | Data Rate per Lane | Protocol Capability |
|---|---|---|---|---|
| QSFP-DD | 4 | 8 | 28Gbps | User Configurable, includes 10/25/40/100G Ethernet |
| Ultraport SlimSAS | 1 | 8 | 25Gbps | OpenCAPI |
| Firefly | 1 | 4 | 28Gbps | User Configurable |
Other I/O Interfaces
USB (front and rear sockets) board management (built-in JTAG)
Isolated PPS Timing Input
Software
TBC
| Ordering Information | ||
|---|---|---|
| ADM-PCIE-9V5(x) | ||
| Parameter | code | Parameter Description |
| FPGA Select | x | blank=Standard COTS product with XCVU9P-3, |
| Note | Other options are available, please contact sales for details. | |
Deliverables
Sales Questions
For any sales questions regarding the ADM-PCIE-9V5, please e-mail us at:
Technical Support
For any technical questions regarding Alpha-Data products please e-mail us at:
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ADM-PCIE-9V5