The XRM2-ADC-S11B is an XRM2 I/O Module, providing one Analog to Digital converter with 12-bit resolution and sampling rates up to 2500Msps.
Aimed at IF/RF Signal Sampling, the sampling clock can be sourced from either an external clock source or from a clock generated within the attached FPGA board. A programmable input attenuator can be used to vary the full scale input level over a 15 dB range. An Auxiliary I/O port is provided for use as a trigger input and general purpose signaling. The XRM2 communicates to the FPGA via a JESD204B high speed interface.
Alpha Data XRM2 I/O Module
|Code||Cooling Option||Operating Temp.||Storage Temp.|
|AC1||Air Cooled Industrial||-40°C||+70°C||-55°C||+100°C|
Operating Humidity range:
Up to 95% (non-condensing)
FCC 47CFR Part 2
EN55022:2010 Equipment ClassB
For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.
Or read: Alpha Data Environment Specification (PDF).
|ANALOG I/O (Front Panel)|
|ADC||1||Single Analog to Digital Converter|
Max Clock Rate: 2500Msps
Levels: full scale (attenuation=0 dB): +5dBm|full scale (attenuation=15 dB): +20dBm
|DISCRETE I/O (Front Panel)|
|External clock input||1||External clock input|
Max Clock Rate: 2500 MHz ( 2000MHz)
Levels: -6dBm to +12dBm (nominal 0 dBm)
Note: Exceeding the maximum voltage limit may result in permanent degradation of converter
|Auxiliary I/O||1||Auxiliary I/O|
Impedance: 4k7Ω (DC Coupled)
Levels: +3V3 LVTTL (DC coupled)
User configurable as inputs or outputs, signals direct to FPGA pins.
Note: signals on these connectors must be restricted to 3V3 logic otherwise damage may result.
|Comms I/O||1||RS422 Communications Interface|
Example UCF, HDL files and Application software are provided with the board.
Sample Product Code:
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